Image sensing elements used in an electronic still camera and the like mainly adopt an interline CCD.
FIG. 6 is a view showing the arrangement of an interline CCD. The interline CCD comprises photodiodes 1 which are two-dimensionally arrayed, read gates 2 which read signal charges stored in the photodiodes 1, vertical transfer portions 3 which vertically transfer signal charges read via the read gates 2, a horizontal transfer portion 4 which horizontally transfers vertically transferred signal charges, and a charge detection portion 6 which is arranged at the horizontal transfer end of the horizontal transfer portion 4 and uses a known floating diffusion amplifier. A portion except the photodiodes 1 is shielded from light by aluminum or the like. Some photodiodes are shielded from light to form a horizontal optical black region 7 which outputs only a dark current component.
FIG. 7 shows conventional driving timings. During the storage period, light incident on the photodiodes 1 is photoelectrically converted and stored. During the storage period, the vertical transfer portions 3 are driven at high speed by high-speed vertical transfer pulses fV1 to fV4 of four phases to drain via the charge detection portion 6 unnecessary charges generated at the vertical transfer portions 3. At time t2, signal charges stored in the photodiodes 1 are read below the fV1 electrodes of the vertical transfer portions via the gates 2 in accordance with a signal read pulse superposed on fV1. Signal charges read to the vertical transfer portions 3 are transferred row by row to the horizontal transfer portion 4 every horizontal scanning in accordance with the vertical transfer pulses fV1 to fV4 of four phases. Signal charges transferred to the horizontal transfer portion 4 are sequentially transferred to the charge detection portion 6 in accordance with horizontal transfer pulses fH1 and fH2 of two phases. Signal charges are converted into a signal voltage, and the voltage is externally output from the image sensing element. The output signal undergoes OB clamping operation and then various processes.
FIG. 8 shows the arrangement of an OB clamping circuit. A signal output from the image sensing element is AC-coupled to a signal processing circuit 802 via a capacitor 801. OB clamping operation is to recover the DC component of an AC-coupled signal by using as a reference an output signal (OB signal) from the horizontal optical black region 7 of the image sensing element. While an OB signal is output, a switch 803 is turned on by an fOB pulse to connect a reference power supply 804 which outputs a reference voltage. As a result, the signal processing circuit side of the capacitor 801 is set to the same voltage as the reference voltage. While a photographed image signal is output, the switch 803 is turned off to generate an image signal by using the OB signal as a reference. After that, various processes are executed to obtain a final image signal.
In the prior art, unnecessary charges at the vertical transfer portions are drained during the storage period. A signal of unnecessary charges is also output from the image sensing element to a pixel output (OB signal) from the horizontal optical black region that serves as a black-level reference signal. Due to the signal output of unnecessary charges, OB clamping malfunctions. In order to prevent this malfunction, an OB clamping pulse is stopped during the storage period, or is prevented from entering the clamping circuit by using a blanking pulse. During this period, the capacitor which holds an input signal at the reference voltage is discharged by an internal resistance or the like, and cannot perform stable OB clamping operation immediately when an original image signal is input. The original reference voltage is set high so as to prevent an image signal from falling below the dynamic range of the circuit even with unstableness of OB clamping operation, resulting in large power consumption.